Lead-Free Wafer Level-Chip Scale Package: Assembly and Reliability

This paper discusses the reliability testing results of a lead-free version of the micro SMD, National Semiconductor’s Wafer Level-Chip Scale Package (WLCSP). The micro SMD, a true wafer scale package has proven to be highly adaptable in the conventional assembly process, requiring no special considerations during the surface mount assembly operation. The current micro SMD utilizes standard Sn/Pb solder bumps as the interconnect medium. Based on evaluations of the various options available for the lead-free solder, micro SMD devices bumped with Sn/Ag/Cu solder were tested during this evaluation. There are two bump sizes currently available for the micro SMD package, a 170-micron bump diameter and a 300-micron bump diameter. This paper addresses the impact of board assembly conditions, package solder type, package bump size, and thermal cycling profiles on the reliability of the lead-free WL-CSPs. This paper will address the initial evaluations on the 170-micron bumped micro SMD packages. Results of this work are used to determine viable combinations of leadfree and eutectic solder. The lead-free version of the micro SMD is in synch with the next packaging evolutionary stage toward a lead-free assembly process. Introduction Market forces, trade restrictions, and customer perceptions rather than environmental realities have driven the lead-free movement. However, it cannot be turned around. Consequently, manufacturers, suppliers, and industry consortia have all been working towards a common acceptable drop-in replacement for the standard eutectic Sn/Pb. Most U.S. and European groups support the use of Sn/Ag/Cu alloys for surface mount applications. For instance, NEMI recommended Sn/3.9Ag/0.6Cu as an industry standard for lead-free solder paste (with Sn/0.7Cu for wave soldering), and is currently assessing its manufacturing and reliability. Similarly, Sn/Ag/Cu alloys have been recommended for solder balls to be used in array packages. A structured approach proposed by National Semiconductor for transitioning from Sn/Pb to lead-free was presented earlier [1]. Sn/Ag/Cu was also selected as the leadfree alloy for the micro SMD package family. In Wafer Level Packages (WLP), the die and package are processed and tested on the wafer, prior to singulation. The technology offers a number of advantages: lower cost with larger wafer size and/or smaller die size; more savings since packaging and test are carried at the wafer level; simplification in shipping and handling logistics; and compatibility with standard surface mount processes. As a result, wafer level packaging has seen wider use lately [2]. The micro SMD from National Semiconductor is one variant of the WLP, namely a Wafer Level-Chip Scale Package. It is currently provided in a standard eutectic (Sn/Pb) solder format [3]. Two versions, the small bump (170-micron ball diameter) and the large bump (300-micron ball diameter) are currently offered. Based on the time-tomarket, which is product-dependent, and the bump size, which is application-driven, the current plan is to release the 300-micron ball lead-free version to production by mid-2002. The 170-micron ball lead-free version will be offered by the third quarter of 2002. This paper focuses on the development of a lead-free, 170-micron ball micro SMD package. Development of the large 300-micron ball lead-free versions will be discussed in the future. Current market trends indicate a migration towards leadfree assemblies. Transitioning to lead-free needs to consider not only the technical aspects of the lead-free choices, but also the supply chain infrastructure, the readiness of customers, and the logistics of dual inventory, namely, Sn/Pb parts and lead-free parts. Inventory sorting will become even more of a challenge, when companies start qualifying and delivering halogen-free packages.